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Beilstein J. Nanotechnol. 2018, 9, 1828–1833, doi:10.3762/bjnano.9.174
Figure 1: Schematic representation of a configuration that implements a tunable FrFT using (a) a convex, and ...
Figure 2: Schematic representation of a segmented gate electrode with segments with (a) equal and (b) unequal...
Figure 3: Schematic representation of a configuration that implements a discrete Fourier transform by discret...